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Tuesday, February 10, 2015

Verilog Behavioral Program for Counters

UP COUNTER (4 BIT) :


module upcount(clk,clr,q);
input clk,clr;
output [3:0]q;
reg [3:0]tmp;
always@(posedge clk or posedge clr)
begin
if(clr)
tmp<=4'b0000;
else
tmp<=tmp+1'b1;
end
assign q=tmp;
endmodule

DOWN COUNTER (4 BIT) :


module downcount(clk,clr,q);
input clk,clr;
output [3:0]q;
reg [3:0]tmp;
always@(posedge clk or posedge clr)
begin
if(clr)
tmp<=4'b1111;
else
tmp<=tmp-1'b1;
end
assign q=tmp;
end module

4 BIT COUNTER:

module fourbitcounter(clk,reset,out);
input clk,reset;
output reg [3:0] out;
always@(posedge reset or negedge clk)
begin
if(reset)
out<=0;
else
out<=out+1'b1;
end
end module

8 BIT COUNTER:

module eightbitcounter(clk,reset,q);
input clk,reset;
output [7:0] q;
wire [3:0] u;
wire [3:0] v;
fourbitcounter f0(clk,reset,u);
fourbitcounter f1(u[3],reset,v);
assign q[3:0]=u;
assign q[7:4]=v;
end module

16 BIT COUNTER

module sixteenbitcounter(clk,reset,a);
input clk,reset;
output [15:0] a;
wire [7:0] s;
wire [7:0] t;
eightbitcounter e0(clk,reset,s);
eightbitcounter e1(s[7],reset,t);
assign a[7:0]=s;
assign a[15:8]=t;
end module

32 BIT COUNTER:

module thirtytwobitccounter(clk,reset,d);
input clk,reset;
output [31:0] d;
wire [15:0] e;
wire [15:0] f;
sixteenbitcounter s0(clk,reset,e);
sixteenbitcounter s1(e[15],reset,f);
assign d[15:0]=e;
assign d[31:16]=f;
endmodule

64 BIT COUNTER:

module sixtyfourbitcounter(clk,reset,g);
input clk,reset;
output [63:0] g;
wire [31:0] h;
wire [31:0] i;
thirtytwobitccounter t0(clk,reset,h);
thirtytwobitccounter t1(h[31],reset,i);
assign g[31:0]=h;
assign g[63:32]=i;
endmodule

128 BIT COUNTER:

module counter_128bit(clk,reset,z);
input clk,reset;
output [127:0] z;
wire [63:0] x;
wire [63:0] y;
sixtyfourbitcounter s0(clk,reset,x);
sixtyfourbitcounter s1(x[63],reset,y);
assign z[63:0]=x;
assign z[127:64]=y;
endmodule

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