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Tuesday, February 10, 2015

Verilog Behavioral Program for Decoder

2 X 4 DECODER :


module decoder(a,en,y);
input [1:0] a;
input en;
output reg [3:0] y;
always@(a or en)
begin
if(!en)
y<=4'b0000;
else
case(a)
2'b00:y<=4'b0001;
2'b01:y<=4'b0010;
2'b10:y<=4'b0100;
2'b11:y<=4'b1000;
endcase
end
endmodule

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