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Tuesday, February 10, 2015

Verilog Behavioral Program for Flip Flops


SR FLIP FLOP :

module srflipflop(clk,S,R,Qnew,Qprev);
input clk,S,R;
output reg Qnew,Qprev=0;
always@(posedge clk)
begin
if(~S&~R)
Qnew<=Qprev;
else if(S&~R)
Qnew<=1;
else if(~S&R)
Qnew<=0;
end
endmodule

D FLIP FLOP :


module dflipflop(D,clk,clr,Q);
input D,clk,clr;
output reg Q=0;
always@(posedge clk or posedge clr)
begin
if(clr)
Q<=0;
else
Q<=D;
end
end module

JK FLIP FLOP :

module jkflipflop(clk,J,K,Q);
input clk,J,K;
output reg Q=0;
always@(negedge clk)
begin
if(J&(~K))
Q<=1;
else if((~J)&K)
Q<=0;
else if (J&K)
Q<=~Q;
end
end module

T FLIP FLOP :

module tflipflop(clk,T,Q);
input clk,T;
output reg Q=0;
always@(negedge clk)
begin
if(T)
Q<=~Q;
end
end module

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