Pages

Tuesday, February 10, 2015

Verilog behavioral program for Half Adder and Full Adder

HALF ADDER :


module halfadder(en,a,sum,carry);
input [1:0] a;
input en;
output reg sum,carry;
always@(en or a)
begin
if(!en)
begin
sum<=0;
carry<=0;
end
else
case(a)
2'b00:
begin
sum<=0;
carry<=0;
end
2'b01:
begin
sum<=1;
carry<=0;
end
2'b10:
begin
sum<=1;
carry<=0;
end
default:
begin
sum<=0;
carry<=1;
end
endcase
end
Endmodule

FULL ADDER :


module fulladder(a,b,cin,en,sum,cout);
input a,b,cin,en;
output reg sum,cout;
reg t1,t2,t3;
always@(a or b or cin or en)
begin
if(!en)
begin
sum<=0;
cout<=0;
end
else
begin
sum<=(a^b)^cin;
t1<=a&b;
t2<=a&cin;
t3<=b&cin;
cout<=(t1|t2)|t3;
end
end
endmodule

1 comments:

Receive all updates via Facebook. Just Click the Like Button Below...