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Tuesday, February 10, 2015

Verilog Behavioral Program for Multiplexers

8X1 MULTIPLEXER :


module eight_to_onemux(s,p,q);
input[2:0]s;
input[7:0]p;
output q;
reg q;
always@(s or p)
begin
case(s)
3'b000:q=p[0];
3'b001:q=p[1];
3'b010:q=p[2];
3'b011:q=p[3];
3'b100:q=p[4];
3'b101:q=p[5];
3'b110:q=p[6];
3'b111:q=p[7];
endcase
end
endmodule

16x1 MULTIPLEXER :

module multiplexer(s,p,q);
input[3:0]s;
input[15:0]p;
output q;
reg q;
always@(s or p)
begin
case(s)
4'b0000:q=p[0];
4'b0001:q=p[1];
4'b0010:q=p[2];
4'b0011:q=p[3];
4'b0100:q=p[4];
4'b0101:q=p[5];
4'b0110:q=p[6];
4'b0111:q=p[7];
4'b1000:q=p[8];
4'b1001:q=p[9];
4'b1010:q=p[10];
4'b1011:q=p[11];
4'b1100:q=p[12];
4'b1101:q=p[13];
4'b1110:q=p[14];
4'b1111:q=p[15];
endcase
end
endmodule

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