Pages

Tuesday, February 10, 2015

Verilog Behavioral Program for Magnitude Comparator

MAGNITUDE COMPARATOR (4 BIT) :


module comp(a,b,equal,greater,lower);
output equal;
reg equal;
output greater;
reg greater;
output reg lower;
input [3:0] a,b;
wire [3:0]a;
always@(a or b)
begin
if(a<b)
begin
equal=0;
lower=1;
greater=0;
end
else if(a==b)
begin
equal=1;
lower=0;
greater=0;
end else
begin
equal=0;
lower=0;
greater=1;
end
end
end module

0 comments:

Post a Comment

Receive all updates via Facebook. Just Click the Like Button Below...