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Tuesday, February 10, 2015

Verilog Behavioral Programs for logic gates implementation

AND GATE :


module andgate(a,b);
input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b11:b=1'b1;
default:b=1'b0;
endcase
end
endmodule

OR GATE :


module orgate(a,b);
input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b00:b=1'b0;
default:b=1'b1;
endcase
end
endmodule

NOT GATE :


module notgate(a,b);
input a;
output reg b;
always@(a)
begin
case(a)
1'b0:b=1'b1;
default:b=1'b0;
endcase
end
endmodule

NAND GATE :


module nandgate(a,b);
input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b00:b=1'b1;
default:b=1'b0;
endcase
end
endmodule

NOR GATE :


module norgate(a,b);
input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b00:b=1'b1;
default:b=1'b0;
endcase
end
endmodul

XOR GATE :

module xorgate(a,b);
input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b00:b=1'b0;
2'b11:b=1'b0;
default:b=1'b1;
endcase
end
endmodule

XNOR GATE :


module xnorgate(a,b);
input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b00:b=1'b1;
2'b11:b=1'b1;
default:b=1'b0;
endcase
end
endmodule

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